A. Walters, P. Athanas,
"A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine,"
Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 333, IEEE Symposium on FPGAs for Custom Computing Machines, 1998.
BibTex
x
@article{
10.1109/FPGA.1998.707941, author = {A. Walters and P. Athanas}, title = {A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1998}, issn = {1082-3409}, pages = {333}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1998.707941}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
x
TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine SN - 1082-3409 SP EP A1 - A. Walters, A1 - P. Athanas, PY - 1998 VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -
A. Walters, P. Athanas, "A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine," fccm, pp.333, IEEE Symposium on FPGAs for Custom Computing Machines, 1998
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