loading...
On Reconfiguring Cache for Computing
Napa California April 21-April 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1999.803704Seventh Annual IEEE Symposium on Fiel ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Hue-Sung Kim, Iowa State University
Arun K. Somani, Iowa State University
Akhilesh Tyagi, Iowa State University
The number of transistors on chip has dramatically increased within the last decade. A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not need all the caches for storage. In addition, some applications have embedded computations with a regular structure. The behavior of the applications is static, which implies that a specialized function unit could be beneficial for the application. This presents an opportunity to explore the use of a part of a cache for performing these regular computations. In this paper, we show one such design to convert a cache into a function unit to improve the performance of an application. A reconfigurable cache takes less area than the area of a cache and a function unit together and imposes no time overhead. In order to convert a cache memory to a function unit, we mapped multi-bit output LUTs into the cache structure. Therefore, the cache can perform computations when it is reconfigured as a function unit.
Index Terms:
reconfigurable hardware, cache, convolution
Citation:
Hue-Sung Kim, Arun K. Somani, Akhilesh Tyagi, "On Reconfiguring Cache for Computing," fccm, pp.296, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999
Usage of this product signifies your acceptance of the Terms of Use.