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A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware
Napa California April 21-April 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1999.803708Seventh Annual IEEE Symposium on Fiel ...
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Miron Abramovici, Bell Labs - Lucent Technologies
Jose T. de Sousa, Bell Labs - Lucent Technologies
Satisfiability (SAT) is a computationally expensive algorithm central to computer science. In this paper, we present a virtual logic algorithm that allows an FPGA based reconfigurable computing platform to process SAT solver circuits much larger than its available capacity. Our algorithm is based on decomposition techniques that create independent sub-problems (pages) that fit the size of the available reconfigurable hardware. Those pages can take turns reusing the platform, and creating a virtual logic environment.
Citation:
Miron Abramovici, Jose T. de Sousa, "A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware," fccm, pp.306, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999
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