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A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA
Napa, California April 17-April 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.2000.9033992000 IEEE Symposium on Field-Programm ...
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M.P. Leong, O.Y.H. Cheung, K.H. Tsoi, P.H.W. Leong, "A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 122, 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, 2000.
 
 
BibTex
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@article{ 10.1109/FPGA.2000.903399,
author = {M.P. Leong and O.Y.H. Cheung and K.H. Tsoi and P.H.W. Leong},
title = {A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA},
journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on},
volume = {0},
year = {2000},
issn = {1082-3409},
pages = {122},
doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.2000.903399},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
TI - A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA
SN - 1082-3409
SP
EP
A1 - M.P. Leong,
A1 - O.Y.H. Cheung,
A1 - K.H. Tsoi,
A1 - P.H.W. Leong,
PY - 2000
VL - 0
JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
ER -
 
M.P. Leong, Chinese University of Hong Kong
O.Y.H. Cheung, Chinese University of Hong Kong
K.H. Tsoi, Chinese University of Hong Kong
P.H.W. Leong, Chinese University of Hong Kong
A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-serial architecture to perform multiplication modulo 216 + 1, the implementation occupies a minimal amount of hardware. The bit-serial architecture enabled the algorithm to be deeply pipelined to achieve a system clock rate of 125MHz. An implementation on a Xilinx Virtex XCV300-4 was successfully tested, delivering a throughput of 500Mb/sec. With an XCV1000-6 device, the estimated performance is 2.35Gb/sec, three orders of magnitude faster than a software implementation on a 450MHz Intel Pentium II. This design is suitable for applications in on-line encryption for high-speed networks.
Citation:
M.P. Leong, O.Y.H. Cheung, K.H. Tsoi, P.H.W. Leong, "A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA," fccm, pp.122, 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, 2000
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