loading...
Hardware Accelerator for Subgraph Isomorphism Problems
Napa, California April 17-April 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.2000.9034172000 IEEE Symposium on Field-Programm ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Shuichi Ichikawa, Toyohashi University of Technology
Lerdtanaseangtham Udorn, Toyohashi University of Technology
Kouji Konishi, Toyohashi University of Technology
Many applications can be modeled as subgraph isomorphism problem, which is generally NP-complete. This paper presents an algorithm that is suited for hardware implementation. The prototype accelerator that operates at 16.5 MHz on Lucent ORCA 2C15A FPGA outperforms the software implementation of Ullmann's algorithm on 400 MHz Pentium II by 10 times in the best case.
Citation:
Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi, "Hardware Accelerator for Subgraph Isomorphism Problems," fccm, pp.283, 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, 2000
Usage of this product signifies your acceptance of the Terms of Use.


Suggestions