loading...
Customising Floating-Point Designs
Napa, California September 22-September 24
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.2002.110669810th Annual IEEE Symposium on Field-P ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Altaf Abdul Gaffar, Imperial College
Wayne Luk, Imperial College
Peter Y. K. Cheung, Imperial College
Nabeel Shirazi, Xilinx, Inc.
This paper describes a method for customising the representation of floating-point numbers that exploits the flexibility of reconfigurable hardware. The method determines the appropriate size of mantissa and exponent for each operation in a design, so that a cost function with a given error specification for the output relative to a reference representation can be satisfied. Currently our tool, which adopts an iterative implementation of this method, supports single- or double-precision floating-point representation as the reference representation. It produces customised floating-point formats with arbitrary-sized mantissa and exponent. Results show that, for calculations involving large dynamic ranges, our method can achieve significant hardware reduction and speed improvement with respect to a design adopting the reference representation.
Citation:
Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, "Customising Floating-Point Designs," fccm, pp.315, 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'02), 2002
Usage of this product signifies your acceptance of the Terms of Use.


Suggestions