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Compiling Policy Descriptions into Reconfigurable Firewall Processors
Napa, California April 09-April 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.2003.122724011th Annual IEEE Symposium on Field-P ...
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T.K. Lee, Imperial College
S. Yusuf, Imperial College
W. Luk, Imperial College
M. Sloman, Imperial College
E. Lupu, Imperial College
N. Dulay, Imperial College
We describe a framework for capturing firewall requirements as high-level descriptions based on the policy specification language Ponder. The framework provides abstraction from hardware implementation while allowing performance control through constraints. Our hardware compilation strategy for such descriptions involves a rule reduction step to produce a hardware firewall rule representation. Three main methods have also been developed for resource optimisation: partitioning, elimination, and sharing. A case study involving five sets of filter rules indicates that it is possible to reduce 67-80% of hardware resources over techniques based on regular content-addressable memory, and 24-63% over methods based on irregular content-addressable memory.
Citation:
T.K. Lee, S. Yusuf, W. Luk, M. Sloman, E. Lupu, N. Dulay, "Compiling Policy Descriptions into Reconfigurable Firewall Processors," fccm, pp.39, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003
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