Hardware-in-the-Loop Evolution of a 3-bit Multiplier

Napa, California April 20-April 23

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http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.39

12th Annual IEEE Symposium on Field-P ...

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	Gregory V. Larchev, Jason D. Lohn, "Hardware-in-the-Loop Evolution of a 3-bit Multiplier," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 277-278, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004.

	BibTex	x
	@article{ 10.1109/FCCM.2004.39, author = {Gregory V. Larchev and Jason D. Lohn}, title = {Hardware-in-the-Loop Evolution of a 3-bit Multiplier}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2230-0}, pages = {277-278}, doi = {http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.39}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Hardware-in-the-Loop Evolution of a 3-bit Multiplier SN - 0-7695-2230-0 SP277 EP278 A1 - Gregory V. Larchev, A1 - Jason D. Lohn, PY - 2004 KW - null VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

Gregory V. Larchev, NASA Ames Research Center, Moffett Field, CA

Jason D. Lohn, NASA Ames Research Center, Moffett Field, CA

In our project, we focused on evolving a 3x3-bit multiplier from scratch. On an actual mission, our method would assume a dual-redundant FPGA system whereby the faulty FPGA undergoes evolution to recover its functionality while the redundant FPGA maintains proper functionality during evolution on the faulty FPGA. Thus after a fault is detected, redundancy is lost for a short period of time and then restored.

Citation:

Gregory V. Larchev, Jason D. Lohn, "Hardware-in-the-Loop Evolution of a 3-bit Multiplier," fccm, pp.277-278, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004

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