This paper describes the package of test bench code required to verify the Algotronix' AES IP Core. Several authors (see the references in [Two Approaches for a Single Chip FPGA Implementation of an Encryptor/Decrytor AES Core]) have published papers detailing the implementation of the Advanced Encryption Standard (AES) on FPGA chips; however, the design goals of this AES core are somewhat different from previous work. Rather than emphasizing performance our design emphasizes portability and customer confidence in the security of the VHDL code.