This contribution is an extension of our work [Architecture Template with Dynamic Buffering for Runtime Reconfigurationof Adaptive Embedded Communication Systems], which introduced distributed buffer schemes for runtime reconfiguration in adaptive processing architectures, e.g., for streaming media applications. We propose a reconfiguration control protocol and depict results for a reference system implementation. With dynamic reconfiguration, area-cost of field-programmable logic (FPL) can be reduced by reuse, and potential for adaptive signal processing techniques can be enabled. The challenge with runtime reconfiguration is the reconfiguration latency. Given the limitation regarding reconfiguration latency with traditional approaches, we proposed distributed buffer schemes. The simulation results show that our approach enables potential for runtime reconfiguration for adaptive signal processing under real-time constraints. The proposed control protocol enables regular structures for modular based dynamic reconfiguration handling. Finally, we present implementation details and results of an architectural system implementation.