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Optimal technology mapping for single output cells
The State University of New York at Buffalo March 16-March 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516017Fifth Great Lakes Symposium on VLSI ( ...
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U. Hinsberger, R. Kolla, "Optimal technology mapping for single output cells," Great Lakes Symposium on VLSI, pp. 14, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
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@article{ 10.1109/GLSV.1995.516017,
author = {U. Hinsberger and R. Kolla},
title = {Optimal technology mapping for single output cells},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {14},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516017},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Optimal technology mapping for single output cells
SN - 1066-1395
SP
EP
A1 - U. Hinsberger,
A1 - R. Kolla,
PY - 1995
KW - Boolean functions; table lookup; field programmable gate arrays; delays; logic CAD; circuit optimisation; optimal technology mapping; single output cells; DAG-mapping; minimum delay mapping; duplication-free mapping; cost functions; logic duplication; AT-tradeoffs; LUT-FPGAs; lookup table; Boolean functions
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
U. Hinsberger, Lehrstuhl fur Tech. Inf., Wurzburg Univ., Germany
R. Kolla, Lehrstuhl fur Tech. Inf., Wurzburg Univ., Germany
This paper presents a new approach to technology mapping for arbitrary technologies with single output cells. It overcomes the restrictions of tree-mapping based methods. Optimal algorithms for special cases of DAG-mapping are presented: for minimum delay mapping and for duplication-free mapping under a class of simple cost functions (including area and delay). Heuristics for duplication of logic and for AT-tradeoffs are developed and applied to LUT-FPGAs.
Index Terms:
Boolean functions; table lookup; field programmable gate arrays; delays; logic CAD; circuit optimisation; optimal technology mapping; single output cells; DAG-mapping; minimum delay mapping; duplication-free mapping; cost functions; logic duplication; AT-tradeoffs; LUT-FPGAs; lookup table; Boolean functions
Citation:
U. Hinsberger, R. Kolla, "Optimal technology mapping for single output cells," glsvlsi, pp.14, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
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