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Bus minimization and scheduling of multi-chip systems
The State University of New York at Buffalo March 16-March 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516021Fifth Great Lakes Symposium on VLSI ( ...
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M. Sheliga, E. Hsing-Mean Sha, "Bus minimization and scheduling of multi-chip systems," Great Lakes Symposium on VLSI, pp. 40, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
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@article{ 10.1109/GLSV.1995.516021,
author = {M. Sheliga and E. Hsing-Mean Sha},
title = {Bus minimization and scheduling of multi-chip systems},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {40},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516021},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Bus minimization and scheduling of multi-chip systems
SN - 1066-1395
SP
EP
A1 - M. Sheliga,
A1 - E. Hsing-Mean Sha,
PY - 1995
KW - multichip modules; circuit layout CAD; scheduling; signal flow graphs; logic CAD; bus minimization; scheduling; polynomial time algorithm; multi-chip module design; algorithm efficiency; signal flow graphs
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
M. Sheliga, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
E. Hsing-Mean Sha, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms.
Index Terms:
multichip modules; circuit layout CAD; scheduling; signal flow graphs; logic CAD; bus minimization; scheduling; polynomial time algorithm; multi-chip module design; algorithm efficiency; signal flow graphs
Citation:
M. Sheliga, E. Hsing-Mean Sha, "Bus minimization and scheduling of multi-chip systems," glsvlsi, pp.40, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
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