Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks

The State University of New York at Buffalo March 16-March 18

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516025

Fifth Great Lakes Symposium on VLSI ( ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by E. Macii Articles by M. Poncino

	ASCII Text	x
	E. Macii, M. Poncino, "Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks," Great Lakes Symposium on VLSI, pp. 60, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516025, author = {E. Macii and M. Poncino}, title = {Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {60}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516025}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks SN - 1066-1395 SP EP A1 - E. Macii, A1 - M. Poncino, PY - 1995 KW - CMOS logic circuits; combinational circuits; integrated circuit modelling; delays; circuit analysis computing; logic CAD; worst-case power consumption; CMOS circuits; symbolic neural networks; combinational circuits; gate level description; energy dissipation; symbolic domain; algebraic decision diagrams; graph specification VL - 0 JA - Great Lakes Symposium on VLSI ER -

E. Macii, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

M. Poncino, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

In this paper we propose a new approach to the problem of estimating worst-case power consumption of CMOS combinational circuits based on neural models. Given the gate level description of a circuit, we build the corresponding neural network, we store it, we calculate the energy dissipated by the network and, finally, we derive the power dissipated by the original circuit. All the operations above are executed in the symbolic domain; that is, Algebraic Decision Diagrams are used to represent and manipulate the graph specification of the neural network modeling the circuit. We present preliminary results to show the feasibility of the method.

Index Terms:

CMOS logic circuits; combinational circuits; integrated circuit modelling; delays; circuit analysis computing; logic CAD; worst-case power consumption; CMOS circuits; symbolic neural networks; combinational circuits; gate level description; energy dissipation; symbolic domain; algebraic decision diagrams; graph specification

Citation:

E. Macii, M. Poncino, "Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks," glsvlsi, pp.60, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.