loading...
Coding a terminated bus for low power
The State University of New York at Buffalo March 16-March 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516027Fifth Great Lakes Symposium on VLSI ( ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
M.R. Stan, W.P. Burleson, "Coding a terminated bus for low power," Great Lakes Symposium on VLSI, pp. 70, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
x
 
@article{ 10.1109/GLSV.1995.516027,
author = {M.R. Stan and W.P. Burleson},
title = {Coding a terminated bus for low power},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {70},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516027},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Coding a terminated bus for low power
SN - 1066-1395
SP
EP
A1 - M.R. Stan,
A1 - W.P. Burleson,
PY - 1995
KW - error correction codes; random-access storage; encoding; decoding; system buses; pull-up terminators; power dissipation; bus liner; limited-weight codes; parallel terminated buses; Rambus; perfect k/2-limited weight code; nonperfect 3-limited weight code
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
M.R. Stan, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
W.P. Burleson, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Coding was proposed as a general method of decreasing power dissipation for the I/O. Lower power dissipation can be obtained by using extra bus liner for coding the data. This paper presents an application of the general theory of limited-weight codes for a class of parallel terminated buses with pull-up terminators (e.g. Rambus). Power dissipation on such a bus-line is larger for a logical 1 and it follows that patterns with few 1s should be chosen. A perfect k/2-limited weight code equivalent to the previously proposed Bus-Invert method and a novel non-perfect 3-limited weight code are described. Both codes can be algorithmically generated and practical issues related to their implementation on the Rambus are discussed.
Index Terms:
error correction codes; random-access storage; encoding; decoding; system buses; pull-up terminators; power dissipation; bus liner; limited-weight codes; parallel terminated buses; Rambus; perfect k/2-limited weight code; nonperfect 3-limited weight code
Citation:
M.R. Stan, W.P. Burleson, "Coding a terminated bus for low power," glsvlsi, pp.70, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
Usage of this product signifies your acceptance of the Terms of Use.