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Circuit/architecture for low-power high-performance 32-bit adder
The State University of New York at Buffalo March 16-March 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516028Fifth Great Lakes Symposium on VLSI ( ...
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I.S. Abu-Khater, A. Bellaouar, M.I. Elmasry, R.H. Yan, "Circuit/architecture for low-power high-performance 32-bit adder," Great Lakes Symposium on VLSI, pp. 74, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
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@article{ 10.1109/GLSV.1995.516028,
author = {I.S. Abu-Khater and A. Bellaouar and M.I. Elmasry and R.H. Yan},
title = {Circuit/architecture for low-power high-performance 32-bit adder},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {74},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516028},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Circuit/architecture for low-power high-performance 32-bit adder
SN - 1066-1395
SP
EP
A1 - I.S. Abu-Khater,
A1 - A. Bellaouar,
A1 - M.I. Elmasry,
A1 - R.H. Yan,
PY - 1995
KW - adders; CMOS logic circuits; integrated circuit design; circuit optimisation; logic design; adder; conditional sum architecture; CPL-like logic implementation; power supply voltage; minimum size; optimized speed; CMOS; 32 bit; 1 to 3.3 V
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
I.S. Abu-Khater, VLSI Res. Group, Waterloo Univ., Ont., Canada
A. Bellaouar, VLSI Res. Group, Waterloo Univ., Ont., Canada
M.I. Elmasry, VLSI Res. Group, Waterloo Univ., Ont., Canada
R.H. Yan, VLSI Res. Group, Waterloo Univ., Ont., Canada
A novel 32-bit adder has been designed using a Conditional Sum Adder (CSA) architecture and CPL-like logic implementation. The new implementation outperforms several architectures such as CLA, CS and Manchester which use the CMOS circuit styles (CPL, DPL, TG, static-conventional) in terms of power and speed. This is verified for a range of power supply voltage from 3.3 V down to 1 V. The comparison is carried out for two designs, minimum size and optimized speed.
Index Terms:
adders; CMOS logic circuits; integrated circuit design; circuit optimisation; logic design; adder; conditional sum architecture; CPL-like logic implementation; power supply voltage; minimum size; optimized speed; CMOS; 32 bit; 1 to 3.3 V
Citation:
I.S. Abu-Khater, A. Bellaouar, M.I. Elmasry, R.H. Yan, "Circuit/architecture for low-power high-performance 32-bit adder," glsvlsi, pp.74, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
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