Partitioning transition relations efficiently and automatically

The State University of New York at Buffalo March 16-March 18

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http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516034

Fifth Great Lakes Symposium on VLSI ( ...

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	ASCII Text	x
	Z. Zhou, X. Song, F. Corella, E. Cerny, M. Langevin, "Partitioning transition relations efficiently and automatically," Great Lakes Symposium on VLSI, pp. 106, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516034, author = {Z. Zhou and X. Song and F. Corella and E. Cerny and M. Langevin}, title = {Partitioning transition relations efficiently and automatically}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {106}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516034}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Partitioning transition relations efficiently and automatically SN - 1066-1395 SP EP A1 - Z. Zhou, A1 - X. Song, A1 - F. Corella, A1 - E. Cerny, A1 - M. Langevin, PY - 1995 KW - logic partitioning; logic CAD; graph theory; state estimation; finite state machines; automatic partitioning; state transition relations; multiway decision graphs; abstract implicit state enumeration procedure; automatic verification method; extended finite state machines; register transfer level designs VL - 0 JA - Great Lakes Symposium on VLSI ER -

Z. Zhou, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

X. Song, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

F. Corella, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

E. Cerny, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

M. Langevin, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

Multiway Decision Graphs (MDGs) have been recently proposed as an efficient representation of Extended Finite State Machines (EFSMs), suitable for automatic hardware verification of Register Transfer Level (RTL) designs. We report here on the results of our research into automatic partitioning of state transition relations described using MDGs. The objective is to achieve the maximum possible performance during an abstract implicit state enumeration procedure that is at the basis of our automatic verification method.

Index Terms:

logic partitioning; logic CAD; graph theory; state estimation; finite state machines; automatic partitioning; state transition relations; multiway decision graphs; abstract implicit state enumeration procedure; automatic verification method; extended finite state machines; register transfer level designs

Citation:

Z. Zhou, X. Song, F. Corella, E. Cerny, M. Langevin, "Partitioning transition relations efficiently and automatically," glsvlsi, pp.106, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

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