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Test application time reduction for scan based sequential circuits
The State University of New York at Buffalo March 16-March 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516050Fifth Great Lakes Symposium on VLSI ( ...
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Hao Zheng, K.K. Saluja, R. Jain, "Test application time reduction for scan based sequential circuits," Great Lakes Symposium on VLSI, pp. 188, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
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@article{ 10.1109/GLSV.1995.516050,
author = {Hao Zheng and K.K. Saluja and R. Jain},
title = {Test application time reduction for scan based sequential circuits},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {188},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516050},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Test application time reduction for scan based sequential circuits
SN - 1066-1395
SP
EP
A1 - Hao Zheng,
A1 - K.K. Saluja,
A1 - R. Jain,
PY - 1995
KW - logic testing; sequential circuits; flip-flops; clocks; boundary scan testing; test application time; scan based sequential circuits; partial scan; single clock configuration; nonscan flip-flops; test vector length; nonatomic two-clock scan method; test generation environment
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Hao Zheng, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
K.K. Saluja, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
R. Jain, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
This paper addresses the issue of reducing test application time in sequential circuits with partial scan using a single clock configuration without freezing the state of the non-scan flip-flops. Experimental results show that this technique significantly reduces test application time. Further, we study the effect of ordering the scan flip-flops on the test vector length and also present a non-atomic two-clock scan method which can be easily incorporated in conventional test generation environment.
Index Terms:
logic testing; sequential circuits; flip-flops; clocks; boundary scan testing; test application time; scan based sequential circuits; partial scan; single clock configuration; nonscan flip-flops; test vector length; nonatomic two-clock scan method; test generation environment
Citation:
Hao Zheng, K.K. Saluja, R. Jain, "Test application time reduction for scan based sequential circuits," glsvlsi, pp.188, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
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