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A 1.0ns 64-bits GaAs Adder using Quad tree algorithm
Ames, IA March 22-March 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.4975876th Great Lakes Symposium on VLSI
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Philippe Royannez, Amara Amara, "A 1.0ns 64-bits GaAs Adder using Quad tree algorithm," Great Lakes Symposium on VLSI, pp. 0024, 6th Great Lakes Symposium on VLSI, 1996.
 
 
BibTex
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@article{ 10.1109/GLSV.1996.497587,
author = {Philippe Royannez and Amara Amara},
title = {A 1.0ns 64-bits GaAs Adder using Quad tree algorithm},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1996},
isbn = {0-8186-7502-0},
pages = {0024},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497587},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A 1.0ns 64-bits GaAs Adder using Quad tree algorithm
SN - 0-8186-7502-0
SP
EP
A1 - Philippe Royannez,
A1 - Amara Amara,
PY - 1996
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Abstract: This paper describes a full custom 64.bits adder targeting the VITESSE E/D MESFET process HGaAsIII. This adder which respects a bit slice topology is part of the project of GaAs data-path compiler for ALLIANCE CAD TOOLS. GaAs's specific properties have been exploited in a full custom approach. Original architecture have been used to increase the parallelism of carries' computation. The layout is portable using a symbolic approach and could also be used with other E/D MESFET process.
Citation:
Philippe Royannez, Amara Amara, "A 1.0ns 64-bits GaAs Adder using Quad tree algorithm," glsvlsi, pp.0024, 6th Great Lakes Symposium on VLSI, 1996
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