A Design Exploration Environment

Ames, IA March 22-March 23

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http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497597

6th Great Lakes Symposium on VLSI

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	ASCII Text	x
	J. Wilberg, A. Kuth, R. Camposano, W. Rosenstiel, H.-T. Vierhaus, "A Design Exploration Environment," Great Lakes Symposium on VLSI, pp. 0077, 6th Great Lakes Symposium on VLSI, 1996.

	BibTex	x
	@article{ 10.1109/GLSV.1996.497597, author = {J. Wilberg and A. Kuth and R. Camposano and W. Rosenstiel and H.-T. Vierhaus}, title = {A Design Exploration Environment}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1996}, isbn = {0-8186-7502-0}, pages = {0077}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497597}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - A Design Exploration Environment SN - 0-8186-7502-0 SP EP A1 - J. Wilberg, A1 - A. Kuth, A1 - R. Camposano, A1 - W. Rosenstiel, A1 - H.-T. Vierhaus, PY - 1996 VL - 0 JA - Great Lakes Symposium on VLSI ER -

A. Kuth

The paper describes the design exploration environment of the CASTLE system. The environment allows the exploration of hardware and software for complex processor designs. The exploration is subdivided into the measurement phase and the analysis phase. The measurement phase uses a retargetable compiler to determine the performance for a large number of different processors and different programs. These fine-grained data form the input of the analysis phase. It transforms the data into abstract representations that are visualized for the designer. The results are integrated into an HTML-based framework.

Citation:

J. Wilberg, A. Kuth, R. Camposano, W. Rosenstiel, H.-T. Vierhaus, "A Design Exploration Environment," glsvlsi, pp.0077, 6th Great Lakes Symposium on VLSI, 1996

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