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CMOS Transistor Sizing for Minimization of Energy-Delay Product
Ames, IA March 22-March 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.4976146th Great Lakes Symposium on VLSI
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Citation:
Christophe Tretz, Charles Zukowski, "CMOS Transistor Sizing for Minimization of Energy-Delay Product," glsvlsi, pp.0168, 6th Great Lakes Symposium on VLSI, 1996
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