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Modeling of Shift Register-based ATM Switch
Lafayette, Louisiana February 19-February 24
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1998.665216Great Lakes Symposium on VLSI '98
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Sandeep Agarwal, Fayez El-Guibaly, "Modeling of Shift Register-based ATM Switch," Great Lakes Symposium on VLSI, pp. 146, Great Lakes Symposium on VLSI '98, 1998.
 
 
BibTex
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@article{ 10.1109/GLSV.1998.665216,
author = {Sandeep Agarwal and Fayez El-Guibaly},
title = {Modeling of Shift Register-based ATM Switch},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1998},
issn = {1066-1395},
pages = {146},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1998.665216},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Modeling of Shift Register-based ATM Switch
SN - 1066-1395
SP
EP
A1 - Sandeep Agarwal,
A1 - Fayez El-Guibaly,
PY - 1998
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Sandeep Agarwal, University of Victoria
Fayez El-Guibaly, University of Victoria
In this paper, we present the modeling of shift register-based ATM switch to find the cell loss probability, throughput and delay. The results are compared with other switch architectures based on input queueing, input smoothing, output queueing and completely shared buffering. It is observed that although our switch is an input buffered switch, it's performance is better than other switches based on traditional queueing approaches.
Citation:
Sandeep Agarwal, Fayez El-Guibaly, "Modeling of Shift Register-based ATM Switch," glsvlsi, pp.146, Great Lakes Symposium on VLSI '98, 1998
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