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IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits
Lafayette, Louisiana February 19-February 24
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1998.665243Great Lakes Symposium on VLSI '98
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Hendrawan Soeleman, Purdue University
Dinesh Somasekhar, Purdue University
Kaushik Roy, Purdue University
This paper describes a test method which relies on the actual observation of supply current (IDD) waveforms. The method can be used to supplement the standard IDDQ test method and it can be easily applied to dynamic and low VDD, low Vt CMOS circuits. The method allows us to detect faults which may not be detected by IDDQ test methods, and is sensitive enough to detect potential faults, which do not manifest themselves as functional errors. A simple built-in current sensor, which proves to be adequate in verifying the feasibility of using the IDD waveforms analysis is proposed to safely observe the current waveforms without significantly changing the waveforms.
Index Terms:
IDD Waveforms Analysis, Testing
Citation:
Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy, "IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits," glsvlsi, pp.243, Great Lakes Symposium on VLSI '98, 1998
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