Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM

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http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757373

Ninth Great Lakes Symposium on VLSI

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	Jörg Hilgenstock, Klaus Herrmann, Peter Pirsch, "Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM," Great Lakes Symposium on VLSI, pp. 42, Ninth Great Lakes Symposium on VLSI, 1999.

	BibTex	x
	@article{ 10.1109/GLSV.1999.757373, author = {Jörg Hilgenstock and Klaus Herrmann and Peter Pirsch}, title = {Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {42}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757373}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM SN - 1066-1395 SP EP A1 - Jörg Hilgenstock, A1 - Klaus Herrmann, A1 - Peter Pirsch, PY - 1999 VL - 0 JA - Great Lakes Symposium on VLSI ER -

Jörg Hilgenstock, Universit?t Hannover

Klaus Herrmann, Universit?t Hannover

Peter Pirsch, Universit?t Hannover

A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.

Citation:

Jörg Hilgenstock, Klaus Herrmann, Peter Pirsch, "Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM," glsvlsi, pp.42, Ninth Great Lakes Symposium on VLSI, 1999

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