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A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs
Ann Arbor, Michigan March 04-March 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757399Ninth Great Lakes Symposium on VLSI
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Hideaki Matsuzaki, Toshihiro Itoh, Masafumi Yamamoto, "A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs," Great Lakes Symposium on VLSI, pp. 154, Ninth Great Lakes Symposium on VLSI, 1999.
 
 
BibTex
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@article{ 10.1109/GLSV.1999.757399,
author = {Hideaki Matsuzaki and Toshihiro Itoh and Masafumi Yamamoto},
title = {A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1999},
issn = {1066-1395},
pages = {154},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757399},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs
SN - 1066-1395
SP
EP
A1 - Hideaki Matsuzaki,
A1 - Toshihiro Itoh,
A1 - Masafumi Yamamoto,
PY - 1999
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Hideaki Matsuzaki, NTT System
Toshihiro Itoh, NTT System
Masafumi Yamamoto, NTT System
An RTD (resonant tunneling diode)-based flip-flop circuit with a new configuration is proposed. The circuit features an SCFL interface for both input and output, and achieves high-speed operation with a simplified configuration. The circuit consists of only two RTDs and three HEMTs, and works as a delayed flip-flop (D-FF) with return- to-zero (RZ) mode output. 50 Gbit/s operation is confirmed by SPICE simulation for the SCFL-interfaced D-FF with the proposed configuration. A static binary frequency divider (T-FF) is also designed based on the same concept. It is fabricated by InP-based RTD/HEMT integration technology, and its proper operation of up to 15 GHz is confirmed experimentally.
Citation:
Hideaki Matsuzaki, Toshihiro Itoh, Masafumi Yamamoto, "A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs," glsvlsi, pp.154, Ninth Great Lakes Symposium on VLSI, 1999
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