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A Low Power Charge-Recycling CMOS Clock Buffer
Ann Arbor, Michigan March 04-March 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757422Ninth Great Lakes Symposium on VLSI
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Xiaohui Wang, Wolfgang Porod, "A Low Power Charge-Recycling CMOS Clock Buffer," Great Lakes Symposium on VLSI, pp. 238, Ninth Great Lakes Symposium on VLSI, 1999.
 
 
BibTex
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@article{ 10.1109/GLSV.1999.757422,
author = {Xiaohui Wang and Wolfgang Porod},
title = {A Low Power Charge-Recycling CMOS Clock Buffer},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1999},
issn = {1066-1395},
pages = {238},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757422},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A Low Power Charge-Recycling CMOS Clock Buffer
SN - 1066-1395
SP
EP
A1 - Xiaohui Wang,
A1 - Wolfgang Porod,
PY - 1999
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Xiaohui Wang, University of Notre Dame
Wolfgang Porod, University of Notre Dame
A low power CMOS clock buffer based on charge recy-cling technique is presented. To accomplish the charge recycling process and avoid introducing the extra short circuit current during the recycling phase, an extra switching circuit and control signal are utilized to keep inverters momentarily tri-state. The feasibility of this design and its improved power efficiency are demon-strated by simulations.
Citation:
Xiaohui Wang, Wolfgang Porod, "A Low Power Charge-Recycling CMOS Clock Buffer," glsvlsi, pp.238, Ninth Great Lakes Symposium on VLSI, 1999
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