loading...
An implementation of hash based ATM router chip
Hawaii, USA January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HICSS.1995.37541128th Hawaii International Conference ...
 This Article 
 
PURCHASE ARTICLE: $0
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
D. Raskovic, E. Jovanov, A. Janicijevic, V. Milutinovic, "An implementation of hash based ATM router chip," Hawaii International Conference on System Sciences, pp. 32, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995.
 
 
BibTex
x
 
@article{ 10.1109/HICSS.1995.375411,
author = {D. Raskovic and E. Jovanov and A. Janicijevic and V. Milutinovic},
title = {An implementation of hash based ATM router chip},
journal ={Hawaii International Conference on System Sciences},
volume = {0},
year = {1995},
issn = {1060-3425},
pages = {32},
doi = {http://doi.ieeecomputersociety.org/10.1109/HICSS.1995.375411},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Hawaii International Conference on System Sciences
TI - An implementation of hash based ATM router chip
SN - 1060-3425
SP
EP
A1 - D. Raskovic,
A1 - E. Jovanov,
A1 - A. Janicijevic,
A1 - V. Milutinovic,
PY - 1995
KW - telecommunication network routing; asynchronous transfer mode; file organisation; storage management; telecommunication computing; ATM router chip; hash based; large size routing tables; hardware support; hash-based hardware accelerator; standard RAM
VL - 0
JA - Hawaii International Conference on System Sciences
ER -
 
D. Raskovic, Sch. of Electr. Eng., Belgrade Univ., Serbia
E. Jovanov, Sch. of Electr. Eng., Belgrade Univ., Serbia
A. Janicijevic, Sch. of Electr. Eng., Belgrade Univ., Serbia
V. Milutinovic, Sch. of Electr. Eng., Belgrade Univ., Serbia
Routing in the ATM environment requires fast handling of large size routing tables, forcing high speed network nodes to implement appropriate hardware support for routing. Traditional solution for this problem is to use associative memories; however, for the ATM router this solution may require an excessively large chip area and power consumption. This paper presents an original architecture of the hash-based hardware accelerator which makes use of standard RAM. Results of analytical simulation, and implementation analysis given in the paper indicate the price/performance ratio which is up to an order of magnitude better compared to some of the existing solutions.
Index Terms:
telecommunication network routing; asynchronous transfer mode; file organisation; storage management; telecommunication computing; ATM router chip; hash based; large size routing tables; hardware support; hash-based hardware accelerator; standard RAM
Citation:
D. Raskovic, E. Jovanov, A. Janicijevic, V. Milutinovic, "An implementation of hash based ATM router chip," hicss, pp.32, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995
Usage of this product signifies your acceptance of the Terms of Use.