Branches interrupt the sequential flow of instructions and introduce pipeline bubbles. Branch penalty can be a significant component of effective cpi (cycles per instruction) in multiple instruction issue processors. Two key issues need to be resolved to alleviate this problem: a branch resolution scheme to decide the direction and target of a branch early in the pipeline, thus allowing target instruction fetch to start, and mechanisms to minimize the impact of unpredictable branches. We propose a technique of caching branch target addresses for our fully predicated processor architecture, that would allow the branch decision to be made in the fetch stage of the pipeline. We discuss the impact of different branch target caching policies and cache sizes on the efficiency of branch target address cache. Impact of register-relative branches which may have variable target addresses is considered and a solution is suggested.