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Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors
Hawaii, USA January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HICSS.1995.37538728th Hawaii International Conference ...
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A.E. Eichenberger, S.G. Abraham, "Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors," Hawaii International Conference on System Sciences, pp. 262, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995.
 
 
BibTex
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@article{ 10.1109/HICSS.1995.375387,
author = {A.E. Eichenberger and S.G. Abraham},
title = {Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors},
journal ={Hawaii International Conference on System Sciences},
volume = {0},
year = {1995},
issn = {1060-3425},
pages = {262},
doi = {http://doi.ieeecomputersociety.org/10.1109/HICSS.1995.375387},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Hawaii International Conference on System Sciences
TI - Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors
SN - 1060-3425
SP
EP
A1 - A.E. Eichenberger,
A1 - S.G. Abraham,
PY - 1995
KW - shared memory systems; synchronisation; resource allocation; cache storage; performance evaluation; concurrency control; network contention; fuzzy barriers; scalable shared-memory multiprocessors; overall execution time; parallel region; nondeterministic load imbalance modelling; random replacement policy; processor caches; hit ratio; variance; cyclic access stream; performance improvement; interprocessor synchronization; 64-processor KSR system; Kendall Square Research system; random first-level caches
VL - 0
JA - Hawaii International Conference on System Sciences
ER -
 
A.E. Eichenberger, Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
S.G. Abraham, Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
Proposes an analytical model that quantifies the overall execution time of a parallel region in the presence of non-deterministic load imbalance introduced by network contention and by a random replacement policy in processor caches. We present a novel model that evaluates the expected hit ratio and variance introduced by a cache accessed with a cyclic access stream. We also model the performance improvement of fuzzy barriers, where the synchronization between processors at the end of a parallel region is relaxed. Experiments on a 64-processor KSR (Kendall Square Research) system which has random first-level caches confirms the general nature of the analytic results.
Index Terms:
shared memory systems; synchronisation; resource allocation; cache storage; performance evaluation; concurrency control; network contention; fuzzy barriers; scalable shared-memory multiprocessors; overall execution time; parallel region; nondeterministic load imbalance modelling; random replacement policy; processor caches; hit ratio; variance; cyclic access stream; performance improvement; interprocessor synchronization; 64-processor KSR system; Kendall Square Research system; random first-level caches
Citation:
A.E. Eichenberger, S.G. Abraham, "Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors," hicss, pp.262, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995
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