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Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration
Madrid, Spain February 14-February 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HPCA.2004.1002610th International Symposium on High ...
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Pierre Michaud, IRISA/INRIA
We propose to modify a conventional single-chip multicore so that a sequential program can migrate from one core to another automatically during execution. The goal of execution migration is to take advantage of the overall onchip cache capacity. We introduce the affinity algorithm, a method for distributing cache lines automatically on several caches. We show that on working-sets exhibiting a property called "splittability", it is possible to trade cache misses for migrations. Our experimental results indicate that the proposed method has a potential for improving the performance of certain sequential programs, without degrading significantly the performance of others.
Citation:
Pierre Michaud, "Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration," hpca, pp.186, 10th International Symposium on High Performance Computer Architecture (HPCA'04), 2004
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