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Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
San Jose, CA November 09-November 13
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.12578752003 International Conference on Comp ...
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Hongliang Chang, University of Minnesota
Sachin S. Sapatnekar, University of Minnesota
We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intra-die parameter variations, using a method based on principal component analysis. The method uses a PERT-like circuit graph traversal, and has a run-time that is linear in the number of gates and interconnects, as well as the number of grid partitions used to model spatial correlations. On average, the mean and standard deviation values computed by our method have errors of 0.2% and 0.9%, respectively, in comparison with a Monte Carlo simulation.
Citation:
Hongliang Chang, Sachin S. Sapatnekar, "Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal," iccad, pp.621, 2003 International Conference on Computer-Aided Design (ICCAD '03), 2003
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