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Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm
Austin, Texas October 10-October 13
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.8084231999 IEEE International Conference on ...
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Paul Chang, Brion Keller, Sarala Paliwal, "Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm," Computer Design, International Conference on, pp. 175, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999.
 
 
BibTex
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@article{ 10.1109/ICCD.1999.808423,
author = {Paul Chang and Brion Keller and Sarala Paliwal},
title = {Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm},
journal ={Computer Design, International Conference on},
volume = {0},
year = {1999},
issn = {1063-6404},
pages = {175},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808423},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Design, International Conference on
TI - Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm
SN - 1063-6404
SP
EP
A1 - Paul Chang,
A1 - Brion Keller,
A1 - Sarala Paliwal,
PY - 1999
KW - parallel processing
KW - fault simulation
KW - LBIST
KW - WRPT
KW - logic built in self test
KW - weighted random pattern test
VL - 0
JA - Computer Design, International Conference on
ER -
 
An increase in chip densities has led to a significant increase in test Generation and fault simulation times. Analysis of various test methodologies has shown that Logic Built in Self Test(LBIST) and Weighted Random Pattern Test(WRPT) are a significant portion of the execution time. Several parallel algorithms have been proposed to reduce run times for ATPG. This paper for the first time describes the parallelization of the LBIST and WRPT algorithms. Results on industrial circuits that range in size from 300,000 gates to about 1 million gates are presented. Previous works have published results on parallelization of deterministic testing and simulation for smaller circuits.
Index Terms:
parallel processing, fault simulation, LBIST, WRPT, logic built in self test, weighted random pattern test
Citation:
Paul Chang, Brion Keller, Sarala Paliwal, "Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm," iccd, pp.175, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999
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