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A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders
Austin, Texas October 10-October 13
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.8084321999 IEEE International Conference on ...
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Bong-Il Park, In-Cheol Park, Chong-Min Kyung, "A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders," Computer Design, International Conference on, pp. 243, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999.
 
 
BibTex
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@article{ 10.1109/ICCD.1999.808432,
author = {Bong-Il Park and In-Cheol Park and Chong-Min Kyung},
title = {A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders},
journal ={Computer Design, International Conference on},
volume = {0},
year = {1999},
issn = {1063-6404},
pages = {243},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808432},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Design, International Conference on
TI - A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders
SN - 1063-6404
SP
EP
A1 - Bong-Il Park,
A1 - In-Cheol Park,
A1 - Chong-Min Kyung,
PY - 1999
KW - Multiplier
KW - Booth algorithm
KW - Carry-Save Adder
KW - and Wallace Tree
VL - 0
JA - Computer Design, International Conference on
ER -
 
Bong-Il Park, Korea Advanced Institute of Science and Technology
In-Cheol Park, Korea Advanced Institute of Science and Technology
Chong-Min Kyung, Korea Advanced Institute of Science and Technology
A new parallel array multiplier based on a new circuit called a Weighted Carry-Save Adder(WCSA) is presented in this paper. Each row of the array consists of a (n+3) bit carry-save adder and one WCSA. Since the proposed WCSA enables the multiplier to be very regular as well as to have less operation complexity at the final addition stage than that of conventional implementations, the proposed WCSA is better suited for hardware implementation. Compared with the previous implementations, the proposed multiplier yields an area reduction of 27% for 64x64 multiplication. A 16x16 multiplier implemented in 0.8um CMOS DLM technology functions at more than 60MHz. The chip is 1.04x1.15mm^2 with 7877 transistors.
Index Terms:
Multiplier, Booth algorithm, Carry-Save Adder, and Wallace Tree
Citation:
Bong-Il Park, In-Cheol Park, Chong-Min Kyung, "A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders," iccd, pp.243, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999
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