To meet increasing system performance demands, microprocessor designers continue to expand the amount of cache memory integrated on the processor die. The resulting additional silicon area has the undesirable effects of reducing die yield and increasing die cost. Adding redundancy to the on-chip caches can mitigate the reduced yield but introduces additional penalties in die area and performance. This paper evaluates the area, performance, and yield impact of several different implementations of on- chip cache redundancy in the context of the next member of Motorola's G4 generation of PowerPC processors.