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A Fast Median Filter Using AltiVec
Austin, Texas October 10-October 13
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.8085711999 IEEE International Conference on ...
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Priyadarshan Kolte, Motorola, Incorporated
Roger Smith, Motorola, Incorporated
Wen Su, Motorola, Incorporated
This paper describes the design and implementation of a median filter for graphics images on the Motorola AltiVec architecture. The filter utilizes 16-way SIMD parallelism to filter images at rates of 1.15 cycles/pixel for 3 ? 3 squares and 6.6 cycles/pixel for 5 ? 5 squares. The median filter is based on a new sorting network which sorts N2 numbers (arranged in an N ? N square) by sorting all columns, rows, and diagonal lines in the square. This paper also describes a scheme for efficient testing of the sorting network.
Citation:
Priyadarshan Kolte, Roger Smith, Wen Su, "A Fast Median Filter Using AltiVec," iccd, pp.384, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999
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