Dominance of interconnect parasitics in impacting functionality, performance and reliability in Deep Sub-Micron (DSM) designs is a well known topic. Reduced metal pitches, process variations, new materials for metallization/ dielectrics emphasizes an increased need for an accurate and yet practical methodology for full-chip performance and reliability verification. This paper describes salient features of the methodology used for timing verification, interconnect modeling, coupling compensation, signal electromigration, power network analysis on power distribution networks. Results from the application of this methodology on TMS320C6201 and TMS320C6701 designed in 0.18u technology are discussed.