We present a way to perform hardware/software partitioning of multi-rate systems based on static priority scheduling theory. The problem is described by a set of interacting concurrent tasks with execution deadlines and dependency constraints. The partitioning tries to reduce the hardware costs and communication overheads for tasks allocated to distinct computing resources. The target architecture includes one or two processors communicating through a bus or a double access RAM or one processor and an ASIC 1 . In the latter case, the ASIC could be used as a coprocessor or as an independent component communicating with the processor through a double access RAM.