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Power-Constrained Microprocessor Design
Freiburg, Germany September 16-September 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.11067402002 IEEE International Conference on ...
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H. Peter Hofstee, "Power-Constrained Microprocessor Design," Computer Design, International Conference on, pp. 14, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002.
 
 
BibTex
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@article{ 10.1109/ICCD.2002.1106740,
author = {H. Peter Hofstee},
title = {Power-Constrained Microprocessor Design},
journal ={Computer Design, International Conference on},
volume = {0},
year = {2002},
issn = {1063-6404},
pages = {14},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106740},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Computer Design, International Conference on
TI - Power-Constrained Microprocessor Design
SN - 1063-6404
SP
EP
A1 - H. Peter Hofstee,
PY - 2002
KW - null
VL - 0
JA - Computer Design, International Conference on
ER -
 
H. Peter Hofstee, IBM Microelectronics
Power dissipation and power density have become first-order design constraints, even for high-performance systems. For future designs it will be the dominant constraint. In this paper we suggest a systematic approach to optimizing a processor design under (only) a power constraint. The approach uses the energy-performance ratio (EPR) of the various design parameters as the key to identifying opportunities for improving energy-efficiency.
Citation:
H. Peter Hofstee, "Power-Constrained Microprocessor Design," iccd, pp.14, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002
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