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Physical Planning Of On-Chip Interconnect Architectures
Freiburg, Germany September 16-September 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.11067432002 IEEE International Conference on ...
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Hongyu Chen, University of California at Dan Diego
Bo Yao, University of California at Dan Diego
Feng Zhou, University of California at Dan Diego
Chung-Kuan Cheng, University of California at Dan Diego
Interconnect architecture plays an important role in determining the throughput of meshed communication structures. We assume a mesh structure with uniform communication demand for communication. A multi-commodity flow (MCF) model is proposed to find the throughput for several different routing architectures. The experimental results reveal several trends: 1. The throughput is limited by the capacity of the middle row and column in the mesh, simply enlarging the congested channel cannot produce better throughput. A flexible chip shape provides around 30% throughput improvement over a square chip of equal area. 2. A 45-degree mesh allows 17% throughput improvement over 90-degree mesh and a 90-degree and 45-degree mixed mesh provides 30% throughput improvement. 3. To achieve maximum throughput on a mixed Manhattan and diagonal interconnect architecture, the best ratio of the capacity for diagonal routing layers and the capacity for Manhattan routing layers is 5.6. 4.Incorporating a simplified via model, interleaving diagonal routing layers and Manhattan routing layer is the best way to organize the wiring directions on different layers.
Citation:
Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng, "Physical Planning Of On-Chip Interconnect Architectures," iccd, pp.30, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002
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