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High Level Functional Verification Closure
Freiburg, Germany September 16-September 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.11067532002 IEEE International Conference on ...
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Surrendra Dudani, Jayant Nagda, "High Level Functional Verification Closure," Computer Design, International Conference on, pp. 91, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002.
 
 
BibTex
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@article{ 10.1109/ICCD.2002.1106753,
author = {Surrendra Dudani and Jayant Nagda},
title = {High Level Functional Verification Closure},
journal ={Computer Design, International Conference on},
volume = {0},
year = {2002},
issn = {1063-6404},
pages = {91},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106753},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Computer Design, International Conference on
TI - High Level Functional Verification Closure
SN - 1063-6404
SP
EP
A1 - Surrendra Dudani,
A1 - Jayant Nagda,
PY - 2002
KW - null
VL - 0
JA - Computer Design, International Conference on
ER -
 
Surrendra Dudani, Synopsys, Inc.
Jayant Nagda, Synopsys, Inc.
We present a methodology to obtain high level functional verification closure. We discuss the current advances in critical technologies that are part of the verification closure solution. Within this methodology, assertion specifications are the starting point and central to the collaboration required between various verification tasks to efficiently search for tests and allow automation to proceed. The goal of verification closure is to generate a complete set of tests that meet the design quality criteria established for the design.
Citation:
Surrendra Dudani, Jayant Nagda, "High Level Functional Verification Closure," iccd, pp.91, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002
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