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Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing
Freiburg, Germany September 16-September 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.11067552002 IEEE International Conference on ...
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Alexander Taubin, Boston University
Karl Fant, Theseus Research
John McCardle, Theseus Logic
This paper presents a novel delay-insensitive three dimension pipeline array multiplier. The organization combines deep (gate-Ievel) pipelining of Manchester adders with two dimensional cross-pipeline mesh for multiplicand and multiplier propagation and partial product bits calculation. Fine grain pipelining with elimination of broadcasting and completion trees leads to high-throughput without use of dynamic logic that leaves the door open for further improvement ofperformance.
Citation:
Alexander Taubin, Karl Fant, John McCardle, "Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing," iccd, pp.104, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002
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