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Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm
Freiburg, Germany September 16-September 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.11067602002 IEEE International Conference on ...
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J.-A. Piñeiro, Universidad Santiago de Compostela
M. D. Ercegovac, University of California at Los Angeles
J. D. Bruguera, Universidad Santiago de Compostela
An analysis of the tradeoffs between area and speed for a sequential implementation of a high-radix recurrence for logarithm computation is presented in this paper. The high-radix algorithm is outlined and a sequential architecture is proposed, with the use of selection by rounding of the digits and redundant representation. Estimates of the execution time and total area are obtained for n = 16, 32 and 64 bits of precision and for radix values from r = 8 to r = 1024. An analysis of the tradeoffs between area and speed is presented, showing that the most efficient implementations are obtained for radices r = 256 for 16, 32-bit and r = 128 for 64-bit computations.
Citation:
J.-A. Piñeiro, M. D. Ercegovac, J. D. Bruguera, "Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm," iccd, pp.132, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002
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