A System-Level Solution to Domino Synthesis with 2 GHz Application

Freiburg, Germany September 16-September 18

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http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106765

2002 IEEE International Conference on ...

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	Similar Articles Articles by B. Chappell Articles by X. Wang Articles by P. Patra Articles by P. Saxena Articles by J. Vendrell Articles by S. Gupta Articles by S. Varadarajan Articles by W. Gomes Articles by S. Hussain Articles by H. Krishnamurthy Articles by M. Venkateshmurthy Articles by S. Jain

	ASCII Text	x
	B. Chappell, X. Wang, P. Patra, P. Saxena, J. Vendrell, S. Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain, "A System-Level Solution to Domino Synthesis with 2 GHz Application," Computer Design, International Conference on, pp. 164, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002.

	BibTex	x
	@article{ 10.1109/ICCD.2002.1106765, author = {B. Chappell and X. Wang and P. Patra and P. Saxena and J. Vendrell and S. Gupta and S. Varadarajan and W. Gomes and S. Hussain and H. Krishnamurthy and M. Venkateshmurthy and S. Jain}, title = {A System-Level Solution to Domino Synthesis with 2 GHz Application}, journal ={Computer Design, International Conference on}, volume = {0}, year = {2002}, issn = {1063-6404}, pages = {164}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106765}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - A System-Level Solution to Domino Synthesis with 2 GHz Application SN - 1063-6404 SP EP A1 - B. Chappell, A1 - X. Wang, A1 - P. Patra, A1 - P. Saxena, A1 - J. Vendrell, A1 - S. Gupta, A1 - S. Varadarajan, A1 - W. Gomes, A1 - S. Hussain, A1 - H. Krishnamurthy, A1 - M. Venkateshmurthy, A1 - S. Jain, PY - 2002 KW - null VL - 0 JA - Computer Design, International Conference on ER -

B. Chappell, Intel Corporation

X. Wang, Intel Corporation

P. Patra, Intel Corporation

P. Saxena, Intel Corporation

J. Vendrell, Intel Corporation

S. Gupta, Intel Corporation

S. Varadarajan, Intel Corporation

W. Gomes, Intel Corporation

S. Hussain, Intel Corporation

H. Krishnamurthy, Intel Corporation

M. Venkateshmurthy, Intel Corporation

S. Jain, Intel Corporation

System structure and a taped out 0.18u 2GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.

Citation:

B. Chappell, X. Wang, P. Patra, P. Saxena, J. Vendrell, S. Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain, "A System-Level Solution to Domino Synthesis with 2 GHz Application," iccd, pp.164, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002

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