This paper introduces a new concept for the self test of systems on a chip (SoCs) with embedded processors. We propose hardware- and software-based test strategy. A minimum sized test processor was designed in order to perform on-chip test functions. It?s architecture contains special adopted registers to realize LFSR or MISR functions for pattern decompaction and pattern filtering. High-performance interfaces allow parallel and serial pattern in- and output, and a fast test vector comparison. The architecture is scalable and is based on a standard RISC architecture in order to facilitate the use of standard compilers.