loading...
VLSI Design and Verification of the Imagine Processor
Freiburg, Germany September 16-September 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2002.11067842002 IEEE International Conference on ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Brucek Khailany, Stanford University
William J. Dally, Stanford University
Andrew Chang, Stanford University
Ujval J. Kapasi, Stanford University
Jinyung Namkoong, Stanford University
Brian Towles, Stanford University
The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford Unversity and Texas Instruments in a 1.5V 0.15 ?m process with fivelayers of aluminum metal. The VLSI design, clocking, and verification methodologies for the Imagine processor are presented. These methodologies enabled a small team of graduate students with limited resources to design a high-performance media processor in a modern ASIC flow.
Citation:
Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles, "VLSI Design and Verification of the Imagine Processor," iccd, pp.289, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002
Usage of this product signifies your acceptance of the Terms of Use.