Due to their simplicity transition faults are often used as targets for test generation to detect delay defects. However, one concern documented in the literature is that of overtesting. One of the reasons for overtesting is that DFT approaches, such as scan, change sequentially untestable faults into testable faults. One approach to reducing overtesting is to identify sequentially untestable and redundant faults and not target them during test generation for the circuit with scan. Another application of identifying untestable transition faults is its use in logic optimization. In this work efficient procedures to identify untestable and redundant transition faults in non-scan synchronous sequential circuits are investigated. Experimental results for ISCAS-89 benchmark circuits are presented.