Low Power Adder with Adaptive Supply Voltage

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http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240880

2003 IEEE International Conference on ...

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	ASCII Text	x
	Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy, "Low Power Adder with Adaptive Supply Voltage," Computer Design, International Conference on, pp. 103, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003.

	BibTex	x
	@article{ 10.1109/ICCD.2003.1240880, author = {Hiroaki Suzuki and Woopyo Jeong and Kaushik Roy}, title = {Low Power Adder with Adaptive Supply Voltage}, journal ={Computer Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-6404}, pages = {103}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240880}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - Low Power Adder with Adaptive Supply Voltage SN - 1063-6404 SP EP A1 - Hiroaki Suzuki, A1 - Woopyo Jeong, A1 - Kaushik Roy, PY - 2003 KW - null VL - 0 JA - Computer Design, International Conference on ER -

Hiroaki Suzuki, Purdue University, West Lafayette

Woopyo Jeong, Purdue University, West Lafayette

Kaushik Roy, Purdue University, West Lafayette

Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a low power adder, which adaptively selects supply voltages based on the input vector patterns. We prototyped a 32-bit Ripple Carry Adder and analyzed the power consumption and performance in details. Results show 29% improvement in power consumption over a conventional ripple carry adder with comparable performance.

Citation:

Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy, "Low Power Adder with Adaptive Supply Voltage," iccd, pp.103, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003

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