Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs

San Jose, California October 13-October 15

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http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240915

2003 IEEE International Conference on ...

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	Janusz Rajski, Jerzy Tyszer, "Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs," Computer Design, International Conference on, pp. 331, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003.

	BibTex	x
	@article{ 10.1109/ICCD.2003.1240915, author = {Janusz Rajski and Jerzy Tyszer}, title = {Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs}, journal ={Computer Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-6404}, pages = {331}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240915}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs SN - 1063-6404 SP EP A1 - Janusz Rajski, A1 - Jerzy Tyszer, PY - 2003 KW - null VL - 0 JA - Computer Design, International Conference on ER -

Janusz Rajski, Mentor Graphics Corporation

Jerzy Tyszer, Poznan University of Technology

In its first part, this paper examines various forms of embedded deterministic test with particular emphasis on input stimuli compression and test response compaction schemes. Subsequently, the Embedded Deterministic Test (EDT) scheme, which significantly reduces manufacturing test cost by providing a dramatic reduction in scan test data volume and scan test time, is discussed.

Citation:

Janusz Rajski, Jerzy Tyszer, "Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs," iccd, pp.331, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003

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