In this paper, based on the advantages of both optical transmission and electronic computation, we first provide an O9loglog N) bus cycles parallel algorithm for the medial axis transform of an N x N binary image on a linear array with a reconfigurable pipelined bus sytem using N² processors. By increasing the number of processors, the proposed algorithm can be modified to run in O(loglog_q N) and O(1) bus cycles using qN²2 and N^2+1/\epsilon processors respectively, where 1 \le q \le √N, \epsilon is a constant and \epsilon \ge 1. These results improve on previously known algorithms developed on various parallel computation models.