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16-Bit FP Sub-Word Parallelism to Facilitate Compiler Vectorization and Improve Performance of Image and Media Processing
Montreal, Quebec, Canada August 15-August 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICPP.2004.13279642004 International Conference on Para ...
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Daniel Etiemble, Lionel Lacassagne, "16-Bit FP Sub-Word Parallelism to Facilitate Compiler Vectorization and Improve Performance of Image and Media Processing," Parallel Processing, International Conference on, pp. 540-547, 2004 International Conference on Parallel Processing (ICPP'04), 2004.
 
 
BibTex
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@article{ 10.1109/ICPP.2004.1327964,
author = {Daniel Etiemble and Lionel Lacassagne},
title = {16-Bit FP Sub-Word Parallelism to Facilitate Compiler Vectorization and Improve Performance of Image and Media Processing},
journal ={Parallel Processing, International Conference on},
volume = {0},
year = {2004},
issn = {0190-3918},
pages = {540-547},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICPP.2004.1327964},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Parallel Processing, International Conference on
TI - 16-Bit FP Sub-Word Parallelism to Facilitate Compiler Vectorization and Improve Performance of Image and Media Processing
SN - 0190-3918
SP540
EP547
A1 - Daniel Etiemble,
A1 - Lionel Lacassagne,
PY - 2004
KW - null
VL - 0
JA - Parallel Processing, International Conference on
ER -
 
Daniel Etiemble, University of Paris Sud
Lionel Lacassagne, University of Paris Sud
We consider the implementation of 16-bit floating point instructions on a Pentium 4 and a PowerPC G5 for image and media processing. By measuring the execution time of benchmarks with these new simulated instructions, we show that significant speed-up is obtained compared to 32-bit FP versions. For image processing, the speed-up both comes from doubling the number of operations per SIMD instruction and the better cache behavior with byte storage. For data stream processing with arrays of structures, the speed-up mainly comes from the wider SIMD instructions.
Citation:
Daniel Etiemble, Lionel Lacassagne, "16-Bit FP Sub-Word Parallelism to Facilitate Compiler Vectorization and Improve Performance of Image and Media Processing," icpp, pp.540-547, 2004 International Conference on Parallel Processing (ICPP'04), 2004
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