A genetic algorithm-based system for generating test programs for microprocessor IP cores

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http://doi.ieeecomputersociety.org/10.1109/TAI.2000.889869

12th IEEE International Conference on ...

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	ASCII Text	x
	F. Corno, M. Sonza Reorda, G. Squillero, M. Violante, "A genetic algorithm-based system for generating test programs for microprocessor IP cores," Tools with Artificial Intelligence, IEEE International Conference on, pp. 0195, 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI'00), 2000.

	BibTex	x
	@article{ 10.1109/TAI.2000.889869, author = {F. Corno and M. Sonza Reorda and G. Squillero and M. Violante}, title = {A genetic algorithm-based system for generating test programs for microprocessor IP cores}, journal ={Tools with Artificial Intelligence, IEEE International Conference on}, volume = {0}, year = {2000}, isbn = {0-7695-0909-6}, pages = {0195}, doi = {http://doi.ieeecomputersociety.org/10.1109/TAI.2000.889869}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Tools with Artificial Intelligence, IEEE International Conference on TI - A genetic algorithm-based system for generating test programs for microprocessor IP cores SN - 0-7695-0909-6 SP EP A1 - F. Corno, A1 - M. Sonza Reorda, A1 - G. Squillero, A1 - M. Violante, PY - 2000 KW - automatic test software; microprocessor chips; industrial property; genetic algorithms; electronic engineering computing; genetic algorithm based system; test program generation; microprocessor IP cores; digital systems design trend; design-and-reuse paradigm; intellectual property cores; encrypted gate-level netlist; testability problems; automatic approach; processor cores; genetic algorithms; test program; fault coverage figures; random approach VL - 0 JA - Tools with Artificial Intelligence, IEEE International Conference on ER -

F. Corno, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

M. Sonza Reorda, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

G. Squillero, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

M. Violante, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

Abstract: The current digital systems design trend is quickly moving toward a design-and-reuse paradigm. In particular, intellectual property cores are becoming widely used. Since the cores are usually provided as encrypted gate-level netlist, they raise several testability problems. The authors propose an automatic approach targeting processor cores that, by resorting to genetic algorithms, computes a test program able to attain high fault coverage figures. Preliminary results are reported to assess the effectiveness of our approach with respect to a random approach.

Index Terms:

automatic test software; microprocessor chips; industrial property; genetic algorithms; electronic engineering computing; genetic algorithm based system; test program generation; microprocessor IP cores; digital systems design trend; design-and-reuse paradigm; intellectual property cores; encrypted gate-level netlist; testability problems; automatic approach; processor cores; genetic algorithms; test program; fault coverage figures; random approach

Citation:

F. Corno, M. Sonza Reorda, G. Squillero, M. Violante, "A genetic algorithm-based system for generating test programs for microprocessor IP cores," ictai, pp.0195, 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI'00), 2000

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